1. Field of the Invention
This invention relates to a memory system including parity bits, more particularly, to a memory system and cache memory system, from which multi-bit data is read out successively, in which the parity configuration is improved.
2. Description of Related Art
In recent years, in accompany with the use of multi-bit data in a microprocessor or the like, it becomes necessary, in a memory system, to compose data with multiple bits. In case of processing multi-bit data, it is natural that data reliability is a point of problem. Therefore, such a method as to detect errors at the time of data transfer by the use of parity is widely adopted.
On the other hand, in accompany with high speedization of a microprocessor or the like, it is required that the memory system can read data successively (continuous reading). In case of memory system including parity, it is necessary to perform parity calculation at higher speed.
From such circumstances as aforementioned, in a memory system capable of continuous reading and including parity bits, conventionally, such a memory configuration as shown in FIG. 2 and FIG. 3 is required in whole configuration as shown in a block diagram in FIG. 1.
In FIG. 2, a first memory block MB1 and a second memory block MB2 in the whole configuration shown in FIG. 1 are shown, and in FIG. 3, a third memory block MB3 and a fourth memory block MB4 in the whole configuration shown in FIG. 1 are shown. Each of the first to fourth memory blocks MB1 to MB4 is composed of first to fourth byte memories 1 to 4, first to fourth write/read circuits 19 to 22, first to fourth parity memories 9 to 12, and first to fourth parity calculation circuits 5 to 8.
The memory system shown in FIG. 1, FIG. 2 and FIG. 3 is capable of 4-word continuous reading. One word is one byte (8 bits), and a parity bit of one bit corresponds to one word. The parity bit is calculated and stored when data is written into a memory. At the time when data is read out from a memory, the parity of the content of the data read from the memory is calculated, and by that it is compared with a value of the parity bit corresponding to the data, so that data reliability is guaranteed. At that time, when the parities are not coincided with each other, the fact is informed to the outside.
In a block diagram shown in FIG. 1, FIG. 2 and FIG. 3, arrangement of each part of the memory system is considered.
Each of the first to fourth memories 1 to 4 is composed of 8 rows, and each of them stores each one word of the data of the first to fourth words which are the targets of 4-word continuous reading. Each of the byte memories 1 to 4 is non-destructive read out type.
To each row of each of the byte memories 1 to 4, each one-bit parity bit is so arranged as to be accessed at the same time, and each 8-bit parity bits corresponding to each byte memories 1 to 4 configures each of the first to fourth parity memories 9 to 12.
The parity calculation is performed by the first to fourth parity calculation circuits 5 to 8. Corresponding to the respective words stored in the first to fourth byte memories 1 to 4 in unit of row, and the respective results are made to be stored in the respective parity bits in the same row as the data to which the respective parity memories 9 to 12 corresponds. The first to fourth parity calculation circuits 5 to 8 calculate, at the time when data are read out from the first to fourth byte memories 1 to 4 in unit of row, parities from the contents of the data read out from the respective byte memories 1 to 4, compare these calculation results with the values of the parity bits in the same rows as the data to which the respective parity memories 9 to 12 correspond, and output first to fourth uncoincidence signals 13 to 16.
The first to fourth uncoincidence signals 13 to 16 show that the data read out from the corresponding byte memories 1 to 4 or the values of the parity bits read out from the parity memories 9 to 12 are not reliable, by that they become active when the comparison result are uncoincidence.
These first to fourth uncoincidence signals 13 to 16 are logical-summed by an OR circuit 17 so as to be outputted to the outside as an error signal 18.
The writing and reading of data to and from the first to fourth byte memories 1 to 4 are controlled by the first to fourth write/read circuits 19 to 22, a word select signal 64 outputted from the word select control circuit 23, and a read/write signal 27.
The respective write/read circuits 19 to 22 performs writing or reading data to the respectively corresponding byte memories i to 4 only when writing or reading data is indicated by the word select signal 64 outputted from the word select signal 64.
Next, explanation will be made on the operation of the conventional memory system shown in FIG. 1, FIG. 2 and FIG. 3.
In this memory system, 5-bit address and 8-bit data are used. The higher 3 bits of the 5-bit address specify the same rows of one or the other of the first to fourth byte memories 1 to 4 and the first to fourth parity memories 9 to 12, and the lower 2 bits specify one or the other of the first to fourth byte memories 1 to 4.
When a 5-bit address is inputted from the outside at the time of memory access, the higher 3 bits 24 among the 5-bit address are inputted to the first and second decoders 25 and 26, and the address lower bit 28 of 2 bits is inputted to the word select control circuit 23.
The first and second decoders 25 and 26 have quite the same logical configuration, have different positions on the memory configuration, though. By signals 250 and 260 of 8 bits obtained from the result of decoding of the address higher bits 24, the decoders 25 and 26 specify simultaneously the same rows of the respective byte memories 1 to 4.
When read/write signal 27 indicates reading, all of the contents in the same rows of the first to fourth byte memories 1 to 4 indicated by the signals 250 and 260 outputted from the first and second decoders 25 and 26 are read out and at the same time, they are inputted also to the first to the fourth parity calculation circuits 5 to 8. And the values of the parity bits in the same rows of the first to fourth parity memories 9 to 12 indicated by the first and second decoders 25 and 26 are read out by the respectively corresponding first to fourth parity calculation circuits 5 to 8.
The first to fourth parity calculation circuits 5 to 8 calculate parities of the data read out from the respectively corresponding byte memories 1 to 4, and compare the results with the parity bits read out from the respectively corresponding parity memories 9 to 12. In the case where even only one of the results of the comparison by the first to fourth parity calculation circuits 5 to 8 shows uncoincidence, the corresponding one of the first to fourth uncoincidence signals 13 to 16 becomes active, thereby the error signal 18 which is the output of the OR gate 17 also becomes active.
On the other hand, the address lower bit 28 of 2 bits is inputted to the word select control circuit 23. In this memory system, since 4-word continuous reading is performed, the word select control circuit 23 outputs a word select signal 64 indicating the word read order in accordance with a round robin method from the word indicated by the address lower bit 28.
Specifically, when the address lower bit 28 is "00", they are read from the first, word (first byte memory 1), when "01", from the second word (second byte memory 2), when "10", from the third word (third byte memory 3), and when "11", from the fourth word (fourth byte memory 4) respectively in order.
The data read out in the order of the indication from the first to fourth byte memories 1 to 4 by the corresponding first to fourth write/read circuits 19 to 22 are outputted to a data bus 29. But this operation is performed regardless of the error signal 18. Whether the data read out to the write/read circuits 19 to 22 are valid or invalid is judged outside of the memory system in accordance with the error signal 18.
In this way, in order to perform the continuous reading from the memory system smoothly, conventionally, the respective words are read out at the same time from the first to fourth byte memories 1 to 4 by the respectively corresponding first to fourth write/read circuits 19 to 22, and outputted to the data bus 29 in accordance with the order indicated by the round robin method by the word select control circuit 23. Therefore each of the first to fourth write/read circuits 19 to 22 is configured as a logical circuit corresponding to 8 bits.
When the read/write signal indicates writing, data is written from the data bus 29 to one or the other of the byte memories 1, 2, 3 and 4 to which only the circuit corresponding to the word indicated by the address lower bit 28 among the first to fourth write/read circuits 19 to 22 corresponds.
For example, when the address lower bit 28 is "10", only the third write/read circuit 21 is indicated by the word select signal 64 outputted from the word select control circuit 23. The third write/read circuit. 21 writes the word data on the data bus 29 into a row specified by the second decoder 26 in the third byte memory 3. Then the third parity calculation circuit 7 inputs data outputted in order to be written in the third byte memory 3 by the third write/read circuit 21 and calculate the parity, and writes the result in the parity bit in the row specified by the second decoder 26 of the third parity memory 11.
As aforementioned, in the conventional memory system including parity bits and capable of continuous reading, since it is necessary for the bits which are the targets of the parity calculation to be arranged in positions physically close to each other on a chip from the viewpoint of the limitation of the parity calculation and it is necessary that the memory elements are so arranged as to be able to read all the words at the same time from the view point of the limitation of the continuous reading, the memory configuration is decided from the limitations, leading to low flexibility of the memory configuration.
In such a conventional memory system as aforementioned, since the write/read circuits 19 to 22 are configured as the logical circuits of the number of bits corresponding to the number of bits of the byte memories 1 to 4, their occupied areas on a chip are large and their electric power consumption is large. Such problems become more obvious when a cache memory is configured by using a plurality of such conventional memory systems as aforementioned.
As the inventor has proposed the invention disclosed as Japanese Patent Application Laid-Open No. 3-147038 (1991) in consideration of such problems, explanation will be made on the Japanese Patent Application Laid-Open No. 3-147038 (1991) as the second prior art.
FIG. 4 is a block diagram showing a configuration of a cache memory of the invention disclosed in the aforementioned Japanese Patent Application Laid-Open No. 147038 (1991), and the cache memory is configured in a 4-way set associative method.
In the conventional example, one word is composed of 32 bits.
In FIG. 4, reference numeral 51 designates an address (request address) at a main memory (external memory) not shown in which data to be accessed requested by a data processor, and the address is composed of an address tag 51a, a set select 81b and a word select 51c from the higher side.
Numeral 82 designates an address tag memory composed of n-number of areas (hereinafter, each area is called an entry), in which the address tag 51a of the address 51 of data is stored in each entry. Four address tag memories 82 are provided to correspond to the respective 4 ways.
Numeral 53 designates a valid bit memory similarly composed of n-number of entries, in which data indicating valid/invalid of the data stored in the entries of the corresponding address tag memory 52 are stored. Four valid bit memories 53 are provided to correspond to the respective 4 ways.
Numeral 54 designates a data memory composed of number of entries. This data memory 54 is composed of 4 data areas of 54a, 54b, 54c and 54d each having been divided in unit of word. Further, each data area 54a, 54b, 54c and 54d is divided into areas for 32 bits from 0th bit to 31st bit for one word, and each one bit area is further divided into areas for 4 ways. FIG. 4 schematically shows that the 0th bit of the data area 54a of the word 1 is divided into areas corresponding to the respective ways A, B, C and D. Further, an area of each one way is divided into n number of entries.
Numeral 55 designates a word selector. In this cache memory system, the word selector 55 selects and operates the data areas 54a, 54b, 54c and 54d corresponding to the respective 4 words according to the word select 51c.
Numeral 59 designates a way selector, in which way select lines (in this example, 4 lines) 59a, 59b, 59c and 59d are provided corresponding to the respective ways. The 4 way select lines 59a, 59b, 59c and 59d are selected by a way select signal to be described later, and activated. An area for each way of each of the data area 54a, 54b, 54c and 54d is connected to a sense amplifier 56 and a write circuit 57 to be described later by a signal line through gate respectively. By that the way select lines 59a, 59b, 59c and 59d become active, the respective gates turn on to connect the respective sense amplifiers 56 or the write circuits 57 with the respective areas for the respective ways.
Numeral 58 designates an address tag comparator, which compares the address tag 51a of the request address 1 with data (address tag) stored in the entry specified by the set select 51b of each way of the address tag memory 52. When the comparison result indicates coincidence, the address tag comparator 58 outputs a hit signal. In addition, also four address tag comparators 58 are provided corresponding to the address tag memories 52, that is, to the respective 4 ways, and the way select signal is outputted to the way selector 59 from the address tag comparator 58 in which the comparison result indicates coincidence.
Each sense amplifier 56 is provided in an area for each bit of each of the data areas 54a, 54b, 54c and 54. The sense amplifier 56 amplifies a signal outputted from an area for a way selected by the way select signal, and outputs it to a data bus 60.
Numeral 57 designates a write circuit, and each write circuit 57 is provided in an area for each bit of each of the data areas 54a, 54b, 54c and 54d. The write circuit 57 inputs a signal inputted from the data bus 60 to an area for a way selected by the way select signal so as to write it.
Since the cache memory system disclosed in the Japanese Patent Application Laid-Open No. 3-147038 (1991) is so configured as mentioned above, the number of the sense amplifiers are the "number of bits in one word".times."the number of words", specifically, EQU 32.times.4.
That is to say, in the cache memory in the conventional example, the number of the sense amplifiers is irrespective of the number of ways, and in case of increasing the number of ways, the number of sense amplifiers 56 is not to be increased.
The operation of such a cache memory of 4-way set associative method disclosed in the Japanese Patent Application Laid-Open No. 3-147038 (1991) is as follows.
Of the request address 51, the address tag 51a is inputted to the address tag comparator 58, the set select 51b to the address tag memory 52 and to the respective data areas 54a, 54b, 54c and 54d of the data memory 54, and the word select 51c to the word selector 55.
In each entry of the address tag memory 52 and the data memory 54, an address tag of an address requested from the data processor and a data block of 4 words read from the main memory by the address have been already stored.
Accessing to the address tag memory 52 and the data memory 54 is performed by specifying an entry address by the set select 51b. That is, the address tag stored in the entry of the address tag memory 52 selected by the set select 51b is read out, and given to the address tag comparator 58. And one or the other of the data areas 54a, 54b 54c and 54d of the data memory 54 is selected by the word selector 55 and becomes in an operation state.
For example, the data area 54a corresponding to the word 1 is assumed to be selected by the word select 51c. One entry, that is, a data block for 4 ways is selected by the set select 51b of the area of the word 1 of the data area 54a.
On the other hand, the address tag comparator 58 compares the address tag 51a of the request address 51 being requested at present from the data processor with an address tag read out from the address tag memory 52, and judges whether they are coincident with each other or not. When the result shows coincidence, the address tag comparator 58 outputs a hit signal as well as to output, the way select signal to the way selector 59.
By the way, as aforementioned, since the conventional cache memory system is of 4-way set associative method, four address tag memories 52 and four address tag comparators 53 are provided corresponding to the number of ways respectively. And the data memory 54 is divided into four data areas of 54a, 54b, 54c and 54d in unit of word, in each of which data corresponding to the number of ways are existed.
Accordingly, the address tag memory 52 and the data memory 54 can store four address tags and four data blocks at maximum to the same entries respectively. Since the respective ways of the address tag memory 52 perform the same operations in parallel, when the address tag comparator 58 judges that there is a hit (coincidence), four address tags are referred to at the same time for one entry address. That is, the address tag comparator 58 compares the address tags of the respective ways read out from the address tag memory 52 with the address tag 51a of the request address 51 being requested at present from the data processor for 4 ways at the same time so as to judge hit/cache miss.
On the other hand, in the data memory 54, the data areas 54a, 54b, 54c or 54d corresponding to one or the other words is selected by the word selector 55, and further, data for 4 ways are selected according to the entry address specified by the set select 51b.
When the way selector 59 receives from the address tag comparator 58 a way select signal showing which way has hit, the way selector 59 makes active the corresponding one of the way select lines 59a, 59b, 59c and 59d. Thereby, since the selected way is connected with the sense amplifier 56 and the write circuit 57, the data corresponding to the request address 51 is outputted from the data memory 54 to the sense amplifier 56 so as to be amplified, and outputted to the data bus 60.
In the conventional example as aforementioned, explanation was made on the cache memory of 4-way, however, any number will do for the way number when it is 2 or more.
As aforementioned, in the memory system including conventional parity bits and capable of continuous reading, bits which are the targets of parity calculation must be allocated to memory elements physically close to each other on a chip from the viewpoint of the limitation of the parity calculation, and the memory elements must be arranged so that all the words can be read at the same time from the viewpoint of the limitation of the successive read, thereby, the memory configuration is decided from these limitations, leading to low flexibility of the memory configuration.
In the conventional cache memory disclosed in the Japanese Patent Application Laid-Open No. 3-147038 (1991) dealing with problems of large occupied areas of the write/read circuits on a chip and of large electric power consumption because the write/read circuits, particularly the sense amplifiers are configured as logical circuits by the number corresponding to the number of bits of the byte memories, there is such a problem that the parity configuration is not taken into consideration.